View LTC3567EUF-PBF_3207572.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc3567 1 3567f typical application features applications description high ef ciency usb power manager plus 1a buck-boost converter with i 2 c control the ltc ? 3567 is a highly integrated power management and battery charger ic for li-ion/polymer battery applica- tions. it includes a high ef? ciency current limited switching powerpath manager with automatic load prioritization, a battery charger, an ideal diode, and a high ef? ciency synchronous buck-boost switching regulator. designed speci? cally for usb applications, the ltc3567s switch- ing power manager automatically limits input current to a maximum of either 100ma or 500ma for usb or 1a for adapter-powered applications. the ltc3567s switching input stage transmits nearly all of the 2.5w available from the usb port to the system load with minimal power wasted as heat. this feature allows the ltc3567 to provide more power to the application and eases thermal budgeting constraints in small spaces. the synchronous buck-boost dc/dc can provide up to 1a output current. the ltc3567 is available in a low pro? le 24-pin (4mm 4mm 0.75mm) qfn surface mount package. ltc3567 usb power manager with a 3.3v/1a buck-boost power manager n high ef? ciency switching powerpath ? controller with bat-track ? adaptive output control n programmable usb or wall current limit (100ma/500ma/1a) n full featured li-ion/polymer battery charger n instant-on operation with a discharged battery n 1.5a maximum charge current n internal 180m ideal diode plus external ideal diode controller powers load in battery mode n low no-load i q when powered from bat (<30a) 1a buck-boost dc/dc n high ef? ciency (1a i out ) n 2.25mhz constant frequency operation n low no-load quiescent current (~13a) n zero shutdown current n i 2 c control of all functions n hdd based mp3 players, pda, gps, pmp products n other usb based handheld products l , lt, ltc and ltm are registered trademarks of linear technology corporation. powerpath and bat-track are a trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 6522118 and 6404251. switching regulator ef? ciency to system load (p out /p bus ) sw v out = bat + 300mv other dc/dcs 3.3v/20ma always on ldo 3.3v/1a hdd from ac adapter from usb v out1 3567 ta01 swcd1 swab1 v in1 ldo3v3 bat gate v out ntc v bus clprog prog v c1 fb1 ltc3567 en1 scl sda dv cc chrg chrgen digital control i 2 c serial interface t + li-ion 3.01k 2k 0.1f 100k 100k 4.7f 3.3h 10f 1f 1f 10f 2.2h 324k 105k 1.5nf optional i out (a) 0.01 0 efficiency (%) 20 40 60 80 0.1 1 3567 ta01b 100 10 30 50 70 90 bat = 4.2v bat = 3.3v v bus = 5v i bat = 0ma 10x mode
ltc3567 2 3567f pin configuration absolute maximum ratings v bus (transient) t<1ms, duty cycle<1% ...... C0.3v to 7v v bus (static), v in1 , bat, ntc, chrg , dv cc , scl, sda, en1, chrgen ................................. C0.3v to 6v fb1, v c1 .................C0.3v to lesser of 6v or v in1 + 0.3v i clprog ....................................................................3ma i chrg ......................................................................50ma i prog ........................................................................2ma i ldo3v3 ...................................................................30ma i sw , i bat , i vout ............................................................2a i vout1 , i swab1 , i swcd1 , ............................................2.5a operating temperature range (note 2).... C40c to 85c junction temperature (note 3) ............................. 125c storage temperature range ................... C65c to 125c (note 1) 24 23 22 21 20 19 7 8 9 top view uf package 24-lead (4mm 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 ldo3v3 clprog ntc fb1 v c1 gnd gate gnd chrg prog sda scl en1 chrgen sw v bus v out bat swab1 dv cc v in1 v out1 swcd1 gnd 25 t jmax = 125c, ja = 37c/w exposed pad (pin 25) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking package description temperature range ltc3567euf#pbf ltc3567euf#trpbf 3567 24-lead (4mm 4mm) plastic qfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ electrical characteristics symbol parameter conditions min typ max units powerpath switching regulator v bus input supply voltage 4.35 5.5 v i buslim total input current 1x mode, v out = bat 5x mode, v out = bat 10x mode, v out = bat suspend mode, v out = bat l l l l 87 436 800 0.31 95 460 860 0.38 100 500 1000 0.50 ma ma ma ma i busq v bus quiescent current 1x mode, i out = 0ma 5x mode, i out = 0ma 10x mode, i out = 0ma suspend mode, i out = 0ma 7 15 15 0.044 ma ma ma ma h clprog (note 4) ratio of measured v bus current to clprog program current 1x mode 5x mode 10x mode suspend mode 224 1133 2140 11.3 ma/ma ma/ma ma/ma ma/ma the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v bus = 5v, v in1 = v out1 = 3.8v, v bat = 3.8v, dv cc = 3.3v, r prog = 1k, r clprog = 3.01k, unless otherwise noted.
ltc3567 3 3567f electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v bus = 5v, v in1 = v out1 = 3.8v, v bat = 3.8v, dv cc = 3.3v, r prog = 1k, r clprog = 3.01k, unless otherwise noted. symbol parameter conditions min typ max units i out (powerpath) v out current available before loading bat 1x mode, bat = 3.3v 5x mode, bat = 3.3v 10x mode, bat = 3.3v suspend mode 135 672 1251 0.32 ma ma ma ma v clprog clprog servo voltage in current limit 1x, 5x, 10x modes suspend mode 1.188 100 v mv v uvlo_vbus v bus undervoltage lockout rising threshold falling threshold 3.95 4.30 4.00 4.35 v v v uvlo_vbus-vbat v bus to bat differential undervoltage lockout rising threshold falling threshold 200 50 mv mv v out v out voltage 1x, 5x, 10x modes, 0v < bat < 4.2v, i out = 0ma, battery charger off 3.4 bat+0.3 4.7 v usb suspend mode, i out = 250a 4.5 4.6 4.7 v f osc switching frequency l 1.8 2.25 2.7 mhz r pmos_powerpath pmos on-resistance 0.18 r nmos_powerpath nmos on-resistance 0.30 i peak_powerpath peak switch current limit 1x, 5x modes 10x mode 2 3 a a battery charger v float bat regulated output voltage l 4.179 4.165 4.200 4.200 4.221 4.235 v v i chg constant current mode charge current r prog = 5k 980 185 1022 204 1065 223 ma ma i bat battery drain current v bus > v uvlo , battery charger off, i out = 0a v bus = 0v, i out = 0a (ideal diode mode) 2 3.5 27 5 38 a a v prog prog pin servo voltage 1.000 v v prog_trikl prog pin servo voltage in trickle charge v bat < v trikl 0.100 v v c/10 c/10 threshold voltage at prog 100 mv h prog ratio of i bat to prog pin current 1022 ma/ma i trkl trickle charge current bat < v trkl 100 ma v trkl trickle charge threshold voltage bat rising 2.7 2.85 3.0 v v trkl trickle charge hysteresis voltage 135 mv v rechrg recharge battery threshold voltage threshold voltage relative to v float C75 C100 C125 mv t term safety timer termination timer starts when bat = v float 3.3 4 5 hour t badbat bad battery termination time bat < v trkl 0.42 0.5 0.63 hour h c/10 end of charge indication current ratio (note 5) 0.088 0.1 0.112 ma/ma v chrg chrg pin output low voltage i chrg = 5ma 65 100 mv i chrg chrg pin leakage current v chrg = 5v 1 a
ltc3567 4 3567f electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v bus = 5v, v in1 = v out1 = 3.8v, v bat = 3.8v, dv cc = 3.3v, r prog = 1k, r clprog = 3.01k, unless otherwise noted. symbol parameter conditions min typ max units r on_chg battery charger power fet on resistance (between v out and bat) 0.18 t lim junction temperature in constant temperature mode 110 c ntc v cold cold temperature fault threshold voltage rising threshold hysteresis 75.0 76.5 1.5 78.0 %v bus %v bus v hot hot temperature fault threshold voltage falling threshold hysteresis 33.4 34.9 1.5 36.4 %v bus %v bus v dis ntc disable threshold voltage falling threshold hysteresis 0.7 1.7 50 2.7 %v bus mv i ntc ntc leakage current v ntc = v bus = 5v C50 50 na ideal diode v fwd forward voltage v bus = 0v, i out = 10ma i out = 10ma 2 15 mv mv r dropout internal diode on-resistance, dropout v bus = 0v 0.18 i max_diode internal diode current limit 1.6 a always on 3.3v supply v ldo3v3 regulated output voltage 0ma < i ldo3v3 < 25ma 3.1 3.3 3.5 v r cl_ldo3v3 closed-loop output resistance 4 r ol_ldo3v3 dropout output resistance 23 logic ( chrgen , en1) v il logic low input voltage 0.4 v v ih logic high input voltage 1.2 v i pd_en1 en1 pull-down current 1.6 a i pd_ chrgen chrgen pull-down current 1.6 10 a i 2 c port (note 6) dv cc input supply voltage 1.6 5.5 v i dvcc dv cc current scl/sda = 0khz 0.3 1 a v dvcc_uvlo dv cc uvlo 1.0 v address i 2 c address 0001001[0] v ih , sda, scl input high voltage 70 %dv cc v il , sda, scl input low voltage 30 %dv cc i ih , i il sda, scl input high/low current C1 0 1 a v ol sda sda output low voltage i sda = 3ma 0.4 v f scl clock operating frequency 400 khz t buf bus free time between stop and start condition 1.3 s t hd_sta hold time after (repeated) start condition 0.6 s t su_sta repeated start condition setup time 0.6 s
ltc3567 5 3567f electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v bus = 5v, v in1 = v out1 = 3.8v, v bat = 3.8v, dv cc = 3.3v, r prog = 1k, r clprog = 3.01k, unless otherwise noted. symbol parameter conditions min typ max units t su_sto stop condition setup time 0.6 s t hd_dat (o) data hold time output 0 900 ns t hd_dat (i) data hold time input 0 ns t su_dat data setup time 100 ns t low scl clock low period 1.3 s t high scl clock high period 0.6 s t f clock/data fall time c b = capacitance of one bus line (pf) 20+0.1?c b 300 ns t r clock/data rise time c b = capacitance of one bus line (pf) 20+0.1?c b 300 ns t sp input spike suppression pulse width 50 ns buck-boost regulator v in1 input supply voltage 2.7 5.5 v v outuvlo v out uvlo C v out falling v out uvlo C v out rising v in1 connected to v out through low impedance. switching regulator is disabled in uvlo 2.5 2.6 2.8 2.9 v v f osc oscillator frequency l 1.8 2.25 2.7 mhz i vin1 input current pwm mode, i out1 = 0a burst mode ? operation, i out1 = 0a shutdown 220 13 0 400 20 1 a a a v out1(low) minimum regulated output voltage for burst mode operation or synchronous pwm operation 2.65 2.75 v v out1(high) maximum regulated output voltage 5.50 5.60 v i limf1 forward current limit (switch a) pwm mode l 2 2.5 3 a i peak1(burst) forward burst current limit (switch a) burst mode operation l 200 275 350 ma i zero1(burst) reverse burst current limit (switch d) burst mode operation l C30 0 30 ma i max1(burst) maximum deliverable output current in burst mode operation 2.7v v in1 5.5v, 2.75v v out1 5.5v (note 6) 50 ma v fbhigh1 maximum servo voltage full scale (1,1,1,1) l 0.780 0.800 0.820 v v fblow1 minimum servo voltage zero scale (0,0,0,0) l 0.405 0.425 0.445 v v lsb1 v fb1 servo voltage step size 25 mv i fb1 fb1 input current v fb1 = 0.8v -50 50 na r ds(on)p pmos r ds(on) switches a, d 0.22 r ds(on)n nmos r ds(on) switches b, c 0.17 i leak(p) pmos switch leakage switches a, d C1 1 a i leak(n) nmos switch leakage switches b, c C1 1 a r vout1 v out1 pull-down in shutdown 10 k d buck(max) maximum buck duty cycle pwm mode l 100 % d boost(max) maximum boost duty cycle pwm mode 75 % t ss1 soft-start time 0.5 ms burst mode is a registered trademark of linear technology corporation.
ltc3567 6 3567f electrical characteristics ideal diode v-i characteristics ideal diode resistance vs battery voltage output voltage vs output current (battery charger disabled) usb limited battery charge current vs battery voltage usb limited battery charge current vs battery voltage battery drain current vs battery voltage note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3567e is guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: the ltc3567 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperatures will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 4: total input current is the sum of quiescent current, i vbusq , and measured current given by: v clprog/rclprog ? (h clprog + 1) note 5: h c/10 is expressed as a fraction of measured full charge current with indicated prog resistor. note 6: guaranteed by design. typical performance characteristics forward voltage (v) 0 current (a) 0.6 0.8 1.0 0.16 3567 g01 0.4 0.2 0 0.04 0.08 0.12 0.20 internal ideal diode with supplemental external vishay si2333 pmos internal ideal diode only v bus = 0v v bus = 5v battery voltage (v) 2.7 resistance () 0.15 0.20 0.25 3.9 3567 g02 0.10 0.05 0 3.0 3.3 3.6 4.2 internal ideal diode with supplemental external vishay si2333 pmos internal ideal diode output current (ma) 0 output voltage (v) 4.00 4.25 4.50 800 3567 g03 3.75 3.50 3.25 200 400 600 1000 bat = 4v bat = 3.4v v bus = 5v 5x mode battery voltage (v) 2.7 500 600 700 3.9 3567 g04 400 300 3.0 3.3 3.6 4.2 200 100 0 charge current (ma) v bus = 5v r prog = 1k r clprog = 2.94k 5x usb setting, battery charger set for 1a battery voltage (v) 2.7 0 charge current (ma) 25 50 75 100 125 150 3.0 3.3 3.6 3.9 3567 g05 4.2 v bus = 5v r prog = 1k r clprog = 2.94k 1x usb setting, battery charger set for 1a battery voltage (v) 2.7 battery current ( a) 15 20 25 3.9 3567 g06 10 5 0 3.0 3.3 3.6 4.2 v bus = 0v v bus = 5v (suspend mode) i vout = 0a t a = 25c unless otherwise noted.
ltc3567 7 3567f typical performance characteristics powerpath switching regulator ef? ciency vs output current v bus current vs v bus voltage (suspend) output voltage vs load current in suspend v bus current vs load current in suspend 3.3v ldo output voltage vs load current, v bus = 0v battery charge current vs temperature battery charger float voltage vs temperature low-battery (instant-on) output voltage vs temperature output current (a) 0.01 40 efficiency (%) 50 60 70 80 100 0.1 1 3567 g07 90 5x, 10x mode 1x mode bat = 3.8v battery charging ef? ciency vs battery voltage with no external load (p bat /p bus ) battery voltage (v) 2.7 efficiency (%) 80 90 3.9 3567 g08 70 60 3.0 3.3 3.6 4.2 100 r clprog = 3.01k r prog = 1k i vout = 0ma 5x charging efficiency 1x charging efficiency bus voltage (v) 0 quiescent current ( a) 30 40 50 4 3567 g09 20 10 0 1 2 3 5 bat = 3.8v i vout = 0ma load current (ma) 0 output voltage (v) 4.0 4.5 5.0 0.4 3567 g10 3.5 3.0 2.5 0.1 0.2 0.3 0.5 v bus = 5v bat = 3.3v r clprog = 2.94k load current (ma) 0 v bus current (ma) 0.3 0.4 0.5 0.4 3567 g11 0.2 0.1 0 0.1 0.2 0.3 0.5 v bus = 5v bat = 3.3v r clprog = 2.94k load current (ma) 0 output voltage (v) 3.0 3.2 20 3567 g12 2.8 2.6 5 10 15 25 3.4 bat = 3v bat = 3.1v bat = 3.2v bat = 3.3v bat = 3.6v bat = 3.5v bat = 3.4v bat = 3.9v, 4.2v temperature (c) C40 0 charge current (ma) 100 200 300 400 040 80 120 3567 g13 500 600 C20 20 60 100 thermal regulation r prog = 2k 10x mode temperature (c) C40 float voltage (v) 4.19 4.20 60 3567 g14 4.18 4.17 C15 10 35 85 4.21 temperature (c) C40 output voltage (v) 3.64 3.66 60 3567 g15 3.62 3.60 C15 10 35 85 3.68 bat = 2.7v i vout = 100ma 5x mode t a = 25c unless otherwise noted.
ltc3567 8 3567f typical performance characteristics oscillator frequency vs temperature v bus quiescent current vs temperature v bus quiescent current in suspend vs temperature chrg pin current vs voltage (pull-down state) 3.3v ldo step response (5ma to 15ma) battery drain current vs temperature r ds(on) for buck-boost regulator power switches vs temperature buck-boost regulator current limit vs temperature buck-boost regulator burst mode operation quiescent current temperature (c) C40 frequency (mhz) 2.2 2.4 60 3567 g16 2.0 1.8 C15 10 35 85 2.6 v bus = 5v bat = 3.6v v bus = 0v bat = 3v v bus = 0v bat = 2.7v v bus = 0v temperature (c) C40 quiescent current (ma) 9 12 60 3567 g17 6 3 C15 10 35 85 15 v bus = 5v i vout = 0a 5x mode 1x mode temperature (c) C40 quiescent current ( a) 50 60 60 3567 g18 40 30 C15 10 35 85 70 i vout = 0 a chrg pin voltage (v) 0 chrg pin current (ma) 60 80 100 4 3567 g19 40 20 0 1 2 3 5 v bus = 5v bat = 3.8v i ldo3v3 5ma/div 0ma 20s/div v bat = 3.8v 3567 g20 v ldo3v3 20mv/div ac coupled temperature (c) C40 battery current ( a) 30 40 50 60 3567 g21 20 10 0 C15 10 35 85 bat = 3.8v v bus = 0v buck regulators off temperature (c) C55 0 pmos r ds(on) () nmos r ds(on) () 0.05 0.15 0.20 0.25 C15 25 45 125 3567 g22 0.10 C35 5 65 85 105 0.30 0.10 0.15 0.25 0.30 0.35 0.20 0.40 pmos v in1 = 3v pmos v in1 = 3.6v pmos v in1 = 4.5v nmos v in1 = 3v nmos v in1 = 3.6v nmos v in1 = 4.5v temperature (c) C55 2300 i limf (ma) 2350 2450 2500 2550 C15 25 45 125 3567 g23 2400 C35 5 65 85 105 2600 v in1 = 3v v in1 = 3.6v v in1 = 4.5v temperature (c) C55 11.0 i q (a) 11.5 12.5 13.0 13.5 C15 25 45 125 3567 g24 12.0 C35 5 65 85 105 14.0 v in1 = 3v v in1 = 3.6v v in1 = 4.5v v out1 = 3.3v t a = 25c unless otherwise noted.
ltc3567 9 3567f typical performance characteristics buck-boost regulator pwm mode ef? ciency buck-boost regulator pwm ef? ciency vs v in1 buck-boost regulator vs i load buck-boost regulator load regulation reduction in current deliverability at low v in1 buck-boost regulator load step, 0ma to 300ma pin functions ldo3v3 (pin 1): 3.3v ldo output pin. this pin provides a regulated always-on, 3.3v supply voltage. ldo3v3 gets its power from v out . it may be used for light loads such as a watchdog microprocessor or real time clock. a 1f capacitor is required from ldo3v3 to ground. if the ldo3v3 output is not used it should be disabled by connecting it to v out . clprog (pin 2): usb current limit program and moni- tor pin. a resistor from clprog to ground determines the upper limit of the current drawn from the v bus pin. a fraction of the v bus current is sent to the clprog pin when the synchronous switch of the powerpath switching regulator is on. the switching regulator delivers power until the clprog pin reaches 1.188v. several v bus cur- rent limit settings are available via user input which will typically correspond to the 500ma and the 100ma usb speci? cations. a multilayer ceramic averaging capacitor or r-c network is required at clprog for ? ltering. ntc (pin 3): input to the thermistor monitoring circuits. the ntc pin connects to a batterys thermistor to deter- mine if the battery is too hot or too cold to charge. if the batterys temperature is out of range, charging is paused i load (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3567 g25 0 1 v out1 = 3.3v type 3 compensation burst mode operation curves pwm mode curves v in1 = 3v v in1 = 3.6v v in1 = 4.5v v in1 = 3v v in1 = 3.6v v in1 = 4.5v v in1 (v) 2.7 efficiency (%) 60 80 100 4.3 3567 g26 40 20 50 70 90 30 10 0 3.1 3.5 3.9 4.7 i load = 50ma i load = 200ma i load = 1000ma v out1 = 3.3v type 3 compensation i load (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3567 g27 0 1 v out1 = 5v type 3 compensation burst mode operation curves pwm mode curves v in1 = 3v v in1 = 3.6v v in1 = 4.5v v in1 = 3v v in1 = 3.6v v in1 = 4.5v i load (ma) 1 3.267 v out1 (v) 3.300 3.311 3.333 3.322 10 100 1a 3567 g28 3.289 3.278 v in1 = 3v v in1 = 3.6v v in1 = 4.5v v out1 = 3.3v type 3 compensation v in1 (v) 2.7 0 reduction below 1a (ma) 50 100 150 200 250 300 3.1 3.5 3.9 4.3 3567 g29 4.7 steady state i load start-up with a resistive load start-up with a current source load v out1 = 3.3v type 3 compensation ch1 v out1 ac 100mv/div ch2 i load dc 200ma/div 100s/div v in1 = 4.2v v out1 = 3.3v l = 2.2h c out = 47f 3567 g30 t a = 25c unless otherwise noted.
ltc3567 10 3567f pin functions until it re-enters the valid range. a low drift bias resistor is required from v bus to ntc and a thermistor is required from ntc to ground. if the ntc function is not desired, the ntc pin should be grounded. fb1 (pin 4): feedback input for the (buck-boost) switching regulator. when the regulators control loop is complete, this pin servos to 1 of 16 possible set-points based on the commanded value from the i 2 c serial port. see table 4. v c1 (pin 5): output of the error ampli? er and voltage compensation node for the (buck-boost) switching regulator. external type i or type iii compensation (to fb1) connects to this pin. see applications section for selecting buck-boost loop compensation components. gnd (pin 6, 12): power gnd pins for the buck-boost. swab1 (pin 7): switch node for the (buck-boost) switch- ing regulator. connected to internal power switches a and b. external inductor connects between this node and swcd1. dv cc (pin 8): logic supply for the i 2 c serial port. v in1 (pin 9): power input for the (buck-boost) switching regulator. this pin will generally be connected to v out (pin 20). a 1f (min) mlcc capacitor is recommended on this pin. v out1 (pin 10): regulated output voltage for the (buck- boost) switching regulator. swcd1 (pin 11): switch node for the (buck-boost) switching regulator. connected to internal power switches c and d. external inductor connects between this node and swab1. scl (pin 13): clock input pin for the i 2 c serial port. the i 2 c logic levels are scaled with respect to dv cc . sda (pin 14): data input pin for the i 2 c serial port. the i 2 c logic levels are scaled with respect to dv cc . prog (pin 15): charge current program and charge current monitor pin. connecting a resistor from prog to ground programs the charge current. if suf? cient in- put power is available in constant-current mode, this pin servos to 1v. the voltage on this pin always represents the actual charge current. chrg (pin 16): open-drain charge status output. the chrg pin indicates the status of the battery charger. four possible states are represented by chrg : charging, not charging, unresponsive battery and battery temperature out of range. chrg is modulated at 35khz and switches between a low and high duty cycle for easy recognition by either humans or microprocessors. see table 1. chrg requires a pull-up resistor and/or led to provide indica- tion. gnd (pin 17): gnd pin for usb power manager. gate (pin 18): analog output. this pin controls the gate of an optional external p-channel mosfet transistor used to supplement the ideal diode between v out and bat. the external ideal diode operates in parallel with the internal ideal diode. the source of the p-channel mosfet should be connected to v out and the drain should be connected to bat. if the external ideal diode fet is not used, gate should be left ? oating. bat (pin 19): single cell li-ion battery pin. depending on available v bus power, a li-ion battery on bat will ei- ther deliver power to v out through the ideal diode or be charged from v out via the battery charger. v out (pin 20): output voltage of the switching power- path controller and input voltage of the battery charger. the majority of the portable product should be powered from v out . the ltc3567 will partition the available power between the external load on v out and the internal battery charger. priority is given to the external load and any extra power is used to charge the battery. an ideal diode from bat to v out ensures that v out is powered even if the load exceeds the allotted power from v bus or if the v bus power source is removed. v out should be bypassed with a low impedance ceramic capacitor. v bus (pin 21): primary input power pin. this pin delivers power to v out via the sw pin by drawing controlled current from a dc source such as a usb port or wall adapter. sw (pin 22): power transmission pin for the usb pow- erpath. the sw pin delivers power from v bus to v out via the step-down switching regulator. a 3.3h inductor should be connected from sw to v out .
ltc3567 11 3567f pin functions chrgen (pin 23): logic input. this logic input pin in- dependently enables the battery charger. active low. has a 1.6a internal pull-down current source. this pin is logically ored with its corresponding bit in the i 2 c serial port. en1 (pin 24): logic input. this logic input pin indepen- dently enables the buck-boost switching regulator. active high. has a 1.6a internal pull-down current source. this pin is logically ored with its corresponding bit in the i 2 c serial port. exposed pad (pin 25): ground. buck-boost logic and usb power manager ground connections. the exposed pad should be connected to a continuous ground plane on the printed circuit board directly under the ltc3567. block diagram C + C + + 1.2v 3.6v 0.3v 15mv gnd chrg ilim decode logic i 2 c port swab1 3567 bd 3.3v ldo cc/cv charger charge status v in1 prog bat gate v out ldo3v3 sw v c1 fb1 dv cc scl ntc en1 clprog chrgen chrgen v bus sda 1a, 2.25mhz buck-boost regulator 2.25mhz powerpath buck regulator suspend ldo 500a/2.5ma battery temperature monitor enable mode +C + C + C swcd1 v out1 ideal d/a 4 21 2 3 16 23 24 8 14 13 6, 12, 17, 25 5 4 11 10 7 9 15 19 18 20 22 1
ltc3567 12 3567f timing diagram t su, dat t hd, sta t hd, dat sda scl t su, sta t hd, sta t su, sto 3567 td t buf t low t high start condition repeated start condition stop condition start condition t r t f t sp ack ack 123 address wr 456789123456789123456789 00 01 0 01 0 00010010 a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 ack stop start sda scl data byte a data byte b operation introduction the ltc3567 is a highly integrated power management ic which includes a high ef? ciency switch mode powerpath controller, a battery charger, an ideal diode, an always-on ldo and a 1a buck-boost switching regulator. the entire chip is controllable via an i 2 c serial port. designed speci? cally for usb applications, the powerpath controller incorporates a precision average input current step-down switching regulator to make maximum use of the allowable usb power. because power is conserved, the ltc3567 allows the load current on v out to exceed the current drawn by the usb port without exceeding the usb load speci? cations. the powerpath switching regulator and battery charger communicate to ensure that the input current never vio- lates the usb speci? cations. the ideal diode from bat to v out guarantees that ample power is always available to v out even if there is insuf? - cient or absent power at v bus . an always-on ldo provides a regulated 3.3v from avail- able power at v out . drawing very little quiescent current, this ldo will be on at all times and can be used to supply up to 25ma. the ltc3567 also has a general purpose buck-boost switching regulator, which can be independently enabled via direct digital control or the i 2 c serial port. along with constant frequency pwm mode, the buck-boost regulator has a low power burst-only mode setting for signi? cantly reduced quiescent current under light load conditions. high ef? ciency switching powerpath controller whenever v bus is available and the powerpath switching regulator is enabled, power is delivered from v bus to v out via sw. v out drives both the external load (including the buck-boost regulator) and the battery charger. if the combined load does not exceed the powerpath switching regulators programmed input current limit, v out will track 0.3v above the battery (bat-track). by keeping the voltage across the battery charger low, ef? ciency is optimized because power lost to the linear battery char- ger is minimized. power available to the external load is therefore optimized. if the combined load at v out is large enough to cause the switching power supply to reach the programmed input current limit, the battery charger will reduce its charge current by the amount necessary to enable the external load to be satis? ed. even if the battery charge current is
ltc3567 13 3567f operation figure 1. v out vs bat set to exceed the allowable usb current, the usb speci? ca- tion will not be violated. the switching regulator will limit the average input current so that the usb speci? cation is never violated. furthermore, load current at v out will always be prioritized and only remaining available power will be used to charge the battery. if the voltage at bat is below 3.3v, or the battery is not present and the load requirement does not cause the switch- ing regulator to exceed the usb speci? cation, v out will regulate at 3.6v, thereby providing instant-on operation. if the load exceeds the available power, v out will drop to a voltage between 3.6v and the battery voltage. if there is no battery present when the load exceeds the available usb power, v out can drop toward ground. the power delivered from v bus to v out is controlled by a 2.25mhz constant-frequency step-down switching regulator. to meet the usb maximum load speci? cation, the switching regulator includes a control loop which ensures that the average input current is below the level programmed at clprog. the current at clprog is a fraction (h clprog C1 ) of the v bus current. when a programming resistor and an averaging capacitor are connected from clprog to gnd, the voltage on clprog represents the average input current of the switching regulator. when the input current approaches the programmed limit, clprog reaches v clprog , 1.188v and power out is held constant. the input current is pro- grammed by the b1 and b0 bits of the i 2 c serial port. it can be con? gured to limit average input current to one of several possible settings as well as be deactivated (usb suspend). the input current limit will be set by the v clprog servo voltage and the resistor on clprog according to the following expression: i vbus = i busq + v clprog r clprog ?(h clprog + 1) figure 1 shows the range of possible voltages at v out as a function of battery voltage. ideal diode from bat to v out the ltc3567 has an internal ideal diode as well as a con- troller for an optional external ideal diode. the ideal diode controller is always on and will respond quickly whenever v out drops below bat. if the load current increases beyond the power allowed from the switching regulator, additional power will be pulled from the battery via the internal ideal diode. furthermore, if power to v bus (usb or wall power) is removed, then all of the application power will be provided by the battery via the ideal diode. the transition from input power to battery power at v out will be quick enough to allow only the 10f capacitor to keep v out from drooping. the ideal diode consists of a precision ampli? er that enables a large on- figure 2. ideal diode operation bat (v) 2.4 4.5 4.2 3.9 3.6 3.3 3.0 2.7 2.4 3.3 3.9 3567 f01 2.7 3.0 3.6 4.2 v out (v) no load 300mv forward voltage (mv) (bat C v out ) 0 current (ma) 600 1800 2000 2200 120 240 300 3567 f02 200 1400 1000 400 1600 0 1200 800 60 180 360 480 420 vishay si2333 optional external ideal diode ltc3567 ideal diode on semiconductor mbrm120lt3
ltc3567 14 3567f operation chip p-channel mosfet transistor whenever the voltage at v out is approximately 15mv (v fwd ) below the voltage at bat. the resistance of the internal ideal diode is approxi- mately 180m. if this is suf? cient for the application, then no external components are necessary. however, if more conductance is needed, an external p-channel mosfet transistor can be added from bat to v out . when an external p-channel mosfet transistor is present, the gate pin of the ltc3567 drives its gate for automatic ideal diode control. the source of the external p-chan- nel mosfet should be connected to v out and the drain should be connected to bat. capable of driving a 1nf load, the gate pin can control an external p-channel mosfet transistor having an on-resistance of 40m or lower. suspend ldo if the ltc3567 is con? gured for usb suspend mode, the switching regulator is disabled and the suspend ldo provides power to the v out pin (presuming there is power available to v bus ). this ldo will prevent the battery from running down when the portable product has access to a suspended usb port. regulating at 4.6v, this ldo only becomes active when the switching converter is disabled (suspended). to remain compliant with the usb speci? ca- tion, the input to the ldo is current limited so that it will not exceed the 500a low power suspend speci? cation. if the load on v out exceeds the suspend current limit, the additional current will come from the battery via the ideal diode. 3.3v always-on supply the ltc3567 includes a low quiescent current low drop-out regulator that is always powered. this ldo can be used to provide power to a system pushbutton controller, standby microcontroller or real time clock. designed to deliver up to 25ma, the always-on ldo requires at least a 1f low impedance ceramic bypass capacitor for compensation. the ldo is powered from v out , and therefore will enter dropout at loads less than 25ma as v out falls near 3.3v. if the ldo3v3 output is not used, it should be disabled by connecting it to v out . v bus undervoltage lockout (uvlo) an internal undervoltage lockout circuit monitors v bus and keeps the powerpath switching regulator off until v bus rises above 4.30v and is at least 200mv above the battery voltage. hysteresis on the uvlo turns off the regulator if v bus drops below 4.00v or to within 50mv of bat. when this happens, system power at v out will be drawn from the battery via the ideal diode. figure 3. powerpath block diagram + C + + C 0.3v 1.206v 3.6v clprog i switch /n + C + C 15mv ideal diode pwm and gate drive average input current limit controller average output voltage limit controller constant current constant voltage battery charger + C gate v out sw 3.5v to (bat + 0.3v) to system load optional external ideal diode pmos single cell li-ion 3567 f03 bat v bus to usb or wall adapter + 21 2 19 18 20 22
ltc3567 15 3567f operation battery charger the ltc3567 includes a constant-current/constant-volt- age battery charger with automatic recharge, automatic termination by safety timer, low voltage trickle charging, bad cell detection and thermistor sensor input for out-of- temperature charge pausing. battery preconditioning when a battery charge cycle begins, the battery charger ? rst determines if the battery is deeply discharged. if the battery voltage is below v trkl , typically 2.85v, an automatic trickle charge feature sets the battery charge current to 10% of the programmed value. if the low voltage persists for more than 1/2 hour, the battery charger automatically terminates and indicates via the chrg pin that the battery was unresponsive. once the battery voltage is above 2.85v, the battery charger begins charging in full power constant-current mode. the current delivered to the battery will try to reach 1022v/ r prog . depending on available input power and external load conditions, the battery charger may or may not be able to charge at the full programmed rate. the external load will always be prioritized over the battery charge current. the usb current limit programming will always be observed and only additional power will be available to charge the battery. when system loads are light, battery charge current will be maximized. charge termination the battery charger has a built-in safety timer. when the voltage on the battery reaches the pre-programmed ? oat voltage of 4.200v, the battery charger will regulate the battery voltage and the charge current will decrease naturally. once the battery charger detects that the battery has reached 4.200v, the four hour safety timer is started. after the safety timer expires, charging of the battery will discontinue and no more current will be delivered. automatic recharge after the battery charger terminates, it will remain off drawing only microamperes of current from the battery. if the portable product remains in this state long enough, the battery will eventually self discharge. to ensure that the battery is always topped off, a charge cycle will auto- matically begin when the battery voltage falls below 4.1v. in the event that the safety timer is running when the battery voltage falls below 4.1v, it will reset back to zero. to prevent brief excursions below 4.1v from resetting the safety timer, the battery voltage must be below 4.1v for more than 1.3ms. the charge cycle and safety timer will also restart if the v bus uvlo cycles low and then high (e.g. v bus , is removed and then replaced), or if the battery charger is cycled on and off by either the i 2 c port or the chrgen digital i/o pin. charge current the charge current is programmed using a single resis- tor from prog to ground. 1/1022 th of the battery charge current is sent to prog which will attempt to servo to 1.000v. thus, the battery charge current will try to reach 1022 times the current in the prog pin. the program resistor and the charge current are calculated using the following equations: r prog = 1022v i chg ,i chg = 1022v r prog in either the constant-current or constant-voltage charging modes, the voltage at the prog pin will be proportional to the actual charge current delivered to the battery. there- fore, the actual charge current can be determined at any time by monitoring the prog pin voltage and using the following equation: i bat = v prog r prog ? 1022 in many cases, the actual battery charge current, i bat , will be lower than i chg due to limited input power available and prioritization with the system load drawn from v out . charge status indication the chrg pin indicates the status of the battery charger. four possible states are represented by chrg which in- clude charging, not charging, unresponsive battery, and battery temperature out of range. the signal at the chrg pin can be easily recognized as one of the above four states by either a human or a
ltc3567 16 3567f operation microprocessor. an open-drain output, the chrg pin can drive an indicator led through a current limiting resistor for human interfacing or simply a pull-up resistor for mi- croprocessor interfacing. to make the chrg pin easily recognized by both humans and microprocessors, the pin is either low for charging, high for not charging, or it is switched at high frequency (35khz) to indicate the two possible faults, unresponsive battery and battery temperature out of range. when charging begins, chrg is pulled low and remains low for the duration of a normal charge cycle. when charging is complete, i.e., the bat pin reaches 4.200v and the charge current has dropped to one-tenth of the programmed value, the chrg pin is released (hi-z). if a fault occurs, the pin is switched at 35khz. while switching, its duty cycle is modulated between a high and low value at a very low frequency. the low and high duty cycles are disparate enough to make an led appear to be on or off thus giving the appearance of blinking. each of the two faults has its own unique blink rate for human recognition as well as two unique duty cycles for machine recognition. the chrg pin does not respond to the c/10 threshold if the ltc3567 is in v bus current limit. this prevents false end of charge indications due to insuf? cient power avail- able to the battery charger. table 1 illustrates the four possible states of the chrg pin when the battery charger is active. table 1. chrg signal status frequency modulation (blink) frequency duty cycles charging 0hz 0hz (lo-z) 100% not charging 0hz 0hz (hi-z) 0% ntc fault 35khz 1.5hz at 50% 6.25%, 93.75% bad battery 35khz 6.1hz at 50% 12.5%, 87.5% an ntc fault is represented by a 35khz pulse train whose duty cycle alternates between 6.25% and 93.75% at a 1.5hz rate. a human will easily recognize the 1.5hz rate as a slow blinking which indicates the out-of-range battery temperature while a microprocessor will be able to decode either the 6.25% or 93.75% duty cycles as an ntc fault. if a battery is found to be unresponsive to charging (i.e., its voltage remains below 2.85v for 1/2 hour), the chrg pin gives the battery fault indication. for this fault, a human would easily recognize the frantic 6.1hz fast blink of the led while a microprocessor would be able to decode either the 12.5% or 87.5% duty cycles as a bad battery fault. note that the ltc3567 is a 3-terminal powerpath prod- uct where system load is always prioritized over battery charging. due to excessive system load, there may not be suf? cient power to charge the battery beyond the trickle charge threshold voltage within the bad battery timeout period. in this case, the battery charger will falsely indicate a bad battery. system software may then reduce the load and reset the battery charger to try again. although very improbable, it is possible that a duty cycle reading could be taken at the bright-dim transition (low duty cycle to high duty cycle). when this happens the duty cycle reading will be precisely 50%. if the duty cycle reading is 50%, system software should disqualify it and take a new duty cycle reading. ntc thermistor the battery temperature is measured by placing a nega- tive temperature coef? cient (ntc) thermistor close to the battery pack. to use this feature, connect the ntc thermistor, r ntc , be- tween the ntc pin and ground and a resistor, r nom , from v bus to the ntc pin. r nom should be a 1% resistor with a value equal to the value of the chosen ntc thermistor at 25c (r25). a 100k thermistor is recommended since thermistor current is not measured by the ltc3567 and will have to be budgeted for usb compliance. the ltc3567 will pause charging when the resistance of the ntc thermistor drops to 0.54 times the value of r25 or approximately 54k. for vishay curve 1 thermistor, this corresponds to approximately 40c. if the battery charger is in constant-voltage (? oat) mode, the safety timer also pauses until the thermistor indicates a return to a valid temperature. as the temperature drops, the resistance of the ntc thermistor rises. the ltc3567 is also designed to pause charging when the value of the ntc thermistor increases to 3.25 times the value of r25. for vishay curve 1 this resistance, 325k, corresponds
ltc3567 17 3567f operation to approximately 0c. the hot and cold comparators each have approximately 3c of hysteresis to prevent oscillation about the trip point. grounding the ntc pin disables the ntc charge pausing function. thermal regulation to optimize charging time, an internal thermal feedback loop may automatically decrease the programmed charge current. this will occur if the die temperature rises to approximately 110c. thermal regulation protects the ltc3567 from excessive temperature due to high power operation or high ambient thermal conditions and allows the user to push the limits of the power handling capability with a given circuit board design without risk of damag- ing the ltc3567 or external components. the bene? t of the ltc3567 thermal regulation loop is that charge current can be set according to actual conditions rather than worst-case conditions with the assurance that the battery charger will automatically reduce the current in worst-case conditions. i 2 c interface the ltc3567 may receive commands from a host (mas- ter) using the standard i 2 c 2-wire interface. the timing diagram shows the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources, such as the ltc1694 i 2 c accelerator, are required on these lines. the ltc3567 is a receive-only (slave) device. the i 2 c control signals, sda and scl are scaled internally to the dv cc supply. dv cc should be con- nected to the same power supply as the microcontroller generating the i 2 c signals. the i 2 c port has an undervoltage lockout on the dv cc pin. when the dv cc is below approximately 1v, the i 2 c serial port is cleared and the buck-boost switching regulator is set to full scale. bus speed the i 2 c port is designed to be operated at speeds of up to 400khz. it has built-in timing delays to ensure correct operation when addressed from an i 2 c compliant master device. it also contains input ? lters designed to suppress glitches should the bus become corrupted. start and stop condition a bus master signals the beginning of a communication to a slave device by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. when the master has ? nished communicating with the slave, it issues a stop condition by transitioning sda from low to high while scl is high. the bus is then free for communication with another i 2 c device. byte format each byte sent to the ltc3567 must be eight bits long followed by an extra clock cycle for the acknowledge bit to be returned by the ltc3567. the data should be sent to the ltc3567 most signi? cant bit (msb) ? rst. acknowledge the acknowledge signal is used for handshaking be- tween the master and the slave. an acknowledge (active low) generated by the slave (ltc3567) lets the master know that the latest byte of information was received. the acknowledge related clock pulse is generated by the master. the master releases the sda line (high) during the acknowledge clock cycle. the slave receiver must pull down the sda line during the acknowledge clock pulse so that it remains a stable low during the high period of this clock pulse. slave address the ltc3567 responds to only one 7-bit address which has been factory programmed to 0001001. the lsb of the address byte is 1 for read and 0 for write. this device is write only corresponding to an address byte of 00010010 (0x12). if the correct seven bit address is given but the r/w bit is 1, the ltc3567 will not respond. bus write operation the master initiates communication with the ltc3567 with a start condition and a 7-bit address followed by the write bit r/w = 0. if the address matches that of the ltc3567, the ltc3567 returns an acknowledge. the master should then deliver the most signi? cant data byte. again the ltc3567 acknowledges and the cycle is repeated for
ltc3567 18 3567f operation table 2. i 2 c serial port mapping (defaults 0xff00 in reset state or if dv cc = 0v) a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 reserved for internal use switching regulator voltage (see table 4) disable battery charger buck-boost regulator mode (see table 5) reserved for internal use enable buck-boost regulator input current limit (see table 3) the total of one address byte and two data bytes. each data byte is transferred to an internal holding latch upon the return of an acknowledge. after both data bytes have been transferred to the ltc3567, the master may terminate the communication with a stop condition. alternatively, a repeat-start condition can be initiated by the master and another chip on the i 2 c bus can be addressed. this cycle can continue inde? nitely and the ltc3567 will remember the last input of valid data that it received. once all chips on the bus have been addressed and sent valid data, a global stop condition can be sent and the ltc3567 will update its command latch with the data that it had received. in certain circumstances the data on the i 2 c bus may become corrupted. in these cases the ltc3567 responds appropriately by preserving only the last set of complete data that it has received. for example, assume the ltc3567 has been successfully addressed and is receiving data when a stop condition mistakenly occurs. the ltc3567 will ignore this stop condition and will not respond until a new start condition, correct address, new set of data and stop condition are transmitted. likewise, with only one exception, if the ltc3567 was previously addressed and sent valid data but not updated with a stop, it will respond to any stop that appears on the bus, independent of the number of repeat-starts that have occurred. if a repeat-start is given and the ltc3567 successfully acknowledges its address and ? rst byte, it will not respond to a stop until both bytes of the new data have been received and acknowledged. disabling the i 2 c port the i 2 c serial port can be disabled by grounding the dv cc pin. in this mode, control automatically passes to the individual logic input pins en1 and chrgen . however, with the i 2 c port disabled, the programmable buck-boost switching regulator defaults to a ? xed servo voltage of 0.8v in pwm mode, and the usb input current limit defaults to 1x mode (100ma limit). by default the battery charger will be enabled and the buck-boost will be disabled. table 3. usb current limit settings b1 b0 usb setting 0 0 1x mode (usb 100ma limit) 0 1 10x mode (wall 1a limit) 1 0 suspend 1 1 5x mode (usb 500ma limit) table 4. buck-boost regulator servo voltage a3 a2 a1 a0 switching regulator servo voltage 0 0 0 0 0.425v 0 0 0 1 0.450v 0 0 1 0 0.475v 0 0 1 1 0.500v 0 1 0 0 0.525v 0 1 0 1 0.550v 0 1 1 0 0.575v 0 1 1 1 0.600v 1 0 0 0 0.625v 1 0 0 1 0.650v 1 0 1 0 0.675v 1 0 1 1 0.700v 1 1 0 0 0.725v 1 1 0 1 0.750v 1 1 1 0 0.775v 1 1 1 1 0.800v table 5. buck-boost switching regulator modes b6 switching regulator mode 0 pwm mode 1 burst mode operation
ltc3567 19 3567f operation buck-boost dc/dc switching regulator the ltc3567 contains a 2.25mhz constant-frequency volt- age mode buck-boost switching regulator. the regulator provides up to 1a of output load current. the buck-boost can be programmed to a minimum output voltage of 2.75v and can be used to power a microcontroller core, micro- controller i/o, memory, disk drive, or other logic circuitry. when controlled by i 2 c, the buck-boost has programmable set-points for on-the-? y power savings. to suit a variety of applications, a selectable mode function allows the user to trade off noise for ef? ciency. two modes are available to control the operation of the ltc3567s buck-boost regula- tor. at moderate to heavy loads, the constant frequency pwm mode provides the least noise switching solution. at lighter loads burst mode operation may be selected. the full-scale output voltage is programmed by a user-supplied resistive divider returned to the fb1 pin. an error ampli? er compares the divided output voltage with a reference and adjusts the compensation voltage accordingly until the fb1 has stabilized to the selected reference voltage (0.425v to 0.8v). the buck-boost regulator also includes a soft-start to limit inrush current and voltage overshoot when powering on, short circuit current protection, and switch node slew limiting circuitry for reduced radiated emi. input current limit the input current limit comparator will shut the input pmos switch off once current exceeds 2.5a (typical). the 2.5a input current limit also protects against a grounded v out1 node. output overvoltage protection if the fb1 node were inadvertently shorted to ground, then the output would increase inde? nitely with the maximum current that could be sourced from v in1 . the ltc3567 protects against this by shutting off the input pmos if the output voltage exceeds a 5.6v (typical). low output voltage operation when the output voltage is below 2.65v (typical) during start-up, burst mode operation is disabled and switch d is turned off (allowing forward current through the well diode and limiting reverse current to 0ma). buck-boost regulator pwm operating mode in pwm mode the voltage seen at fb1 is compared to the selected reference voltage (0.425v to 0.8v). from the fb1 voltage an error ampli? er generates an error signal seen at v c1 . this error signal commands pwm waveforms that modulate switches a, b, c, and d. switches a and b operate synchronously as do switches c and d. if v in1 is signi? cantly greater than the programmed v out1 , then the converter will operate in buck mode. in this mode switches a and b will be modulated, with switch d always on (and switch c always off), to step down the input voltage to the programmed output. if v in1 is signi? cantly less than the programmed v out1 , then the converter will operate in boost mode. in this mode switches c and d are modulated, with switch a always on (and switch b always off), to step up the input voltage to the programmed output. if v in1 is close to the programmed v out1 , then the converter will operate in 4-switch mode. in this mode the switches sequence through the pattern of ad, ac, bd to either step the input voltage up or down to the programmed output. buck-boost regulator burst-mode operation in burst mode operation, the buck-boost regulator uses a hysteretic fb1 voltage algorithm to control the output voltage. by limiting fet switching and using a hysteretic control loop, switching losses are greatly reduced. in this mode output current is limited to 50ma typical. while operating in burst mode operation, the output capacitor is charged to a voltage slightly higher than the regulation point. the buck-boost converter then goes into a sleep state, during which the output capacitor provides the load current. the output capacitor is charged by charg- ing the inductor until the input current reaches 275ma typical and then discharging the inductor until the reverse current reaches 0ma typical. this process is repeated until the feedback voltage has charged to 6mv above the regulation point. in the sleep state, most of the regulators circuitry is powered down, helping to conserve battery power. when the feedback voltage drops 6mv below the regulation point, the switching regulator circuitry is pow- ered on and another burst cycle begins. the duration for which the regulator sleeps depends on the load current and output capacitor value. the sleep time decreases as the load current increases. the maximum load current in
ltc3567 20 3567f clprog resistor and capacitor as described in the high ef? ciency switching powerpath controller section, the resistor on the clprog pin deter- mines the average input current limit when the switching regulator is set to either the 1x mode (usb 100ma), the 5x mode (usb 500ma) or the 10x mode. the input cur- rent will be comprised of two components, the current that is used to drive v out and the quiescent current of the switching regulator. to ensure that the usb speci? cation is strictly met, both components of input current should be considered. the electrical characteristics table gives values for quiescent currents in either setting as well as current limit programming accuracy. to get as close to the 500ma or 100ma speci? cations as possible, a 1% resistor should be used. recall that i vbus = i vbusq + v clprog /r clprog ? (h clprog + 1). an averaging capacitor or an r-c combination is required in parallel with the clprog resistor so that the switching regulator can determine the average input current. this network also provides the dominant pole for the feedback loop when current limit is reached. to ensure stability, the capacitor on clprog should be 0.1f or larger. choosing the powerpath inductor because the input voltage range and output voltage range of the powerpath switching regulator are both fairly nar- row, the ltc3567 was designed for a speci? c inductance value of 3.3h. some inductors which may be suitable for this application are listed in table 6. table 6. recommended inductors for powerpath controller inductor type l (h) max i dc (a) max dcr () size in mm (l w h) manufacturer lps4018 3.3 2.2 0.08 3.9 3.9 1.7 coilcraft www.coilcraft.com d53lc db318c 3.3 3.3 2.26 1.55 0.034 0.070 5.0 5.0 3.0 3.8 3.8 1.8 toko www.toko.com we-tpc type m1 3.3 1.95 0.065 4.8 4.8 1.8 wrth elektronik www.we-online.com cdrh6d12 cdrh6d38 3.3 3.3 2.2 3.5 0.0625 0.020 6.7 6.7 1.5 7.0 7.0 4.0 sumida www.sumida.com operation burst mode operation is 50ma. the buck-boost regulator will not go to sleep if the current is greater than 50ma, and if the load current increases beyond this point while in burst mode operation the output will lose regulation. burst mode operation provides a signi? cant improvement in ef? ciency at light loads at the expense of higher output ripple when compared to pwm mode. for many noise- sensitive systems, burst mode operation might be unde- sirable at certain times (i.e., during a transmit or receive cycle of a wireless device), but highly desirable at others (i.e. when the device is in low power standby mode). the b6 bit of the i 2 c port is used to enable or disable burst mode operation at any time, offering both low noise and low power operation when they are needed. buck-boost regulator soft-start operation soft-start is accomplished by gradually increasing the reference voltage input to the error ampli? er over a 0.5ms (typical) period. this limits transient inrush currents during start-up because the output voltage is always in regula- tion. ramping the reference voltage input also limits the rate of increase in the v c1 voltage which helps minimize output overshoot during start-up. a soft-start cycle oc- curs whenever the buck-boost is enabled, or after a fault condition has occurred (thermal shutdown or uvlo). a soft-start cycle is not triggered by changing operating modes. this allows seamless operation when transitioning between burst mode operation and pwm mode. low supply operation the ltc3567 incorporates an undervoltage lockout cir- cuit on v out (connected to v in1 ) which shuts down the buck-boost regulator when v out drops below 2.6v. this uvlo prevents unstable operation. applications information
ltc3567 21 3567f applications information v bus and v out bypass capacitors the style and value of capacitors used with the ltc3567 determine several important parameters such as regulator control-loop stability and input voltage ripple. because the ltc3567 uses a step-down switching power supply from v bus to v out , its input current waveform contains high frequency components. it is strongly recommended that a low equivalent series resistance (esr) multilayer ceramic capacitor be used to bypass v bus . tantalum and aluminum capacitors are not recommended because of their high esr. the value of the capacitor on v bus directly controls the amount of input ripple for a given load cur- rent. increasing the size of this capacitor will reduce the input ripple. to prevent large v out voltage steps during transient load conditions, it is also recommended that a ceramic capaci- tor be used to bypass v out . the output capacitor is used in the compensation of the switching regulator. at least 4f of actual capacitance with low esr are required on v out . additional capacitance will improve load transient performance and stability. multilayer ceramic chip capacitors typically have excep- tional esr performance. mlccs combined with a tight board layout and an unbroken ground plane will yield very good performance and low emi emissions. there are several types of ceramic capacitors available, each having considerably different characteristics. for example, x7r ceramic capacitors have the best voltage and temperature stability. x5r ceramic capacitors have appar- ently higher packing density but poorer performance over their rated voltage and temperature ranges. y5v ceramic capacitors have the highest packing density, but must be used with caution, because of their extreme nonlinear characteristic of capacitance vs voltage. the actual in-circuit capacitance of a ceramic capacitor should be measured with a small ac signal (ideally less than 200mv) as is expected in-circuit. many vendors specify the capacitance vs voltage with a 1v rms ac test signal and as a result overstate the capacitance that the capacitor will present in the application. using similar operating conditions as the application, the user must measure or request from the vendor the actual capacitance to determine if the selected capacitor meets the minimum capacitance that the application requires. buck-boost regulator inductor selection many different sizes and shapes of inductors are avail- able from numerous manufacturers. choosing the right inductor from such a large selection of devices can be overwhelming, but following a few basic guidelines will make the selection process much simpler. the buck-boost converter is designed to work with induc- tors in the range of 1h to 5h. for most applications a 2.2h inductor will suf? ce. larger value inductors reduce ripple current which improves output ripple voltage. lower value inductors result in higher ripple current and improved transient response time. to maximize ef? ciency, choose an inductor with a low dc resistance. for a 3.3v output, ef? ciency is reduced about 3% for a 100m series resis- tance at 1a load current, and about 2% for 300m series resistance at 200ma load current. choose an inductor with a dc current rating at least two times larger than the maximum load current to ensure that the inductor does not saturate during normal operation. if output short circuit is a possible condition, the inductor should be rated to handle the 2.5a maximum peak current speci? ed for the buck-boost converter. different core materials and shapes will change the size/current and price/current relationship of an induc- tor. toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. inductors that are very thin or have a very small volume typically have much higher core and dcr losses, and will not give the best ef- ? ciency. the choice of which style inductor to use often depends more on the price vs size, performance and any radiated emi requirements than on what the ltc3567 requires to operate. the inductor value also has an effect on burst mode op- eration. lower inductor values will cause the burst mode operation switching frequencies to increase. table 7 shows several inductors that work well with the ltc3567s buck-boost regulator. these inductors offer a good compromise in current rating, dcr and physical size. consult each manufacturer for detailed information on their entire selection of inductors.
ltc3567 22 3567f applications information table 7. recommended inductors for buck-boost regulator inductor type l (h) max i dc (a) max dcr () size in mm (l w h) manufacturer lps4018 3.3 2.2 2.2 2.5 0.08 0.07 3.9 3.9 1.7 3.9 3.9 1.7 coilcraft www.coilcraft.com d53lc 2.0 3.25 0.02 5.0 5.0 3.0 toko www.toko.com 7440430022 2.2 2.5 0.028 4.8 4.8 2.8 wrth-elektronik www.we-online.com cdrh4d22/ hp 2.2 2.4 0.044 4.7 4.7 2.4 sumida www.sumida.com sd14 2.0 2.56 0.045 5.2 5.2 1.45 c ooper www.cooper.com buck-boost regulator input/output capacitor selection low esr mlcc capacitors should also be used at both the buck-boost regulator output (v out1 ) and the buck- boost regulator input supply (v in1 ). only x5r or x7r ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. a 22f output capaci- tor is suf? cient for most applications. the buck-boost regulator input supply should be bypassed with a 2.2f capacitor. consult with capacitor manufacturers for de- tailed information on their selection and speci? cations of ceramic capacitors. many manufacturers now offer very thin (<1mm tall) ceramic capacitors ideal for use in height restricted designs. table 8 shows a list of several ceramic capacitor manufacturers. table 8. recommended ceramic capacitor manufacturers manufacturer website avx www.avxcorp.com murata www.murata.com taiyo yuden www.t-yuden.com vishay siliconix www.vishay.com tdk www.tdk.com over-programming the battery charger the usb high power speci? cation allows for up to 2.5w to be drawn from the usb port (5v 500ma). the powerpath switching regulator transforms the voltage at v bus to just above the voltage at bat with high ef? ciency, while limiting power to less than the amount programmed at clprog. in some cases the battery charger may be programmed (with the prog pin) to deliver the maximum safe charging current without regard to the usb speci? cations. if there is insuf? cient current available to charge the battery at the programmed rate, the powerpath regulator will reduce charge current until the system load on v out is satis? ed and the v bus current limit is satis? ed. programming the battery charger for more current than is available will not cause the average input current limit to be violated. it will merely allow the battery charger to make use of all available power to charge the battery as quickly as possible, and with minimal power dissipation within the battery charger. alternate ntc thermistors and biasing the ltc3567 provides temperature quali? ed charging if a grounded thermistor and a bias resistor are connected to ntc. by using a bias resistor whose value is equal to the room temperature resistance of the thermistor (r25) the upper and lower temperatures are pre-programmed to approximately 40c and 0c, respectively (assuming a vishay curve 1 thermistor). the upper and lower temperature thresholds can be ad- justed by either a modi? cation of the bias resistor value or by adding a second adjustment resistor to the circuit. if only the bias resistor is adjusted, then either the upper or the lower threshold can be modi? ed but not both. the other trip point will be determined by the characteristics of the thermistor. using the bias resistor in addition to an adjustment resistor, both the upper and the lower tem- perature trip points can be independently programmed with the constraint that the difference between the upper and lower temperature thresholds cannot decrease. ex- amples of each technique follow. ntc thermistors have temperature characteristics which are indicated on resistance-temperature conversion tables. the vishay-dale thermistor nths0603n011-n1003f, used in the following examples, has a nominal value of 100k and follows the vishay curve 1 resistance-temperature characteristic. in the explanation below, the following notation is used. r25 = value of the thermistor at 25c r ntc|cold = value of thermistor at the cold trip point
ltc3567 23 3567f applications information r ntc|hot = value of thermistor at the hot trip point r cold = ratio of r ntc|cold to r25 r hot = ratio of r ntc|hot to r25 r nom = primary thermistor bias resistor (see figure 4a) r1 = optional temperature range adjustment resistor (see figure 4b) the trip points for the ltc3567s temperature quali? ca- tion are internally programmed at 0.349 ? v bus for the hot threshold and 0.765 ? v bus for the cold threshold. therefore, the hot trip point is set when: r ntc|hot r nom + r ntc|hot ?v bus = 0.349 ? v bus and the cold trip point is set when: r ntc|cold r nom + r ntc|cold ?v bus = 0.765 ? v bus solving these equations for r ntc|cold and r ntc|hot results in the following: r ntc|hot = 0.536?r nom and r ntc|cold = 3.25?r nom by setting r nom equal to r25, the above equations result in r hot = 0.536 and r cold = 3.25. referencing these ratios to the vishay resistance-temperature curve 1 chart gives a hot trip point of about 40c and a cold trip point of about 0c. the difference between the hot and cold trip points is approximately 40c. by using a bias resistor, r nom , different in value from r25, the hot and cold trip points can be moved in either direction. the temperature span will change somewhat due to the nonlinear behavior of the thermistor. the following equations can be used to easily calculate a new value for the bias resistor: r nom = r hot 0.536 ?r25 r nom = r cold 3.25 ?r25 where r hot and r cold are the resistance ratios at the de- sired hot and cold trip points. note that these equations are linked. therefore, only one of the two trip points can be chosen, the other is determined by the default ratios designed in the ic. consider an example where a 60c hot trip point is desired. from the vishay curve 1 r-t characteristics, r hot is 0.2488 at 60c. using the above equation, r nom should be set to 46.4k. with this value of r nom , the cold trip point is about 16c. notice that the span is now 44c rather than the previous 40c. this is due to the decrease in tem- perature gain of the thermistor as absolute temperature increases. the upper and lower temperature trip points can be in- dependently programmed by using an additional bias resistor as shown in figure 4b. the following formulas can be used to compute the values of r nom and r1: r nom = r cold ? r hot 2.714 ?r25 r1 = 0.536 ? r nom ? r hot ?r25 for example, to set the trip points to 0c and 45c with a vishay curve 1 thermistor choose r nom = 3.266 ? 0.4368 2.714 ? 100k = 104.2k the nearest 1% value is 105k r1 = 0.536?105k C 0.4368?100k = 12.6k the nearest 1% value is 12.7k. the ? nal solution is shown in figure 4b and results in an upper trip point of 45c and a lower trip point of 0c. usb inrush limiting when a usb cable is plugged into a portable product, the inductance of the cable and the high-q ceramic input capacitor form an l-c resonant circuit. if the cable does not have adequate mutual coupling or if there is not much impedance in the cable, it is possible for the voltage at the input of the product to reach as high as twice the usb voltage (~10v) before it settles out. to prevent excessive voltage from damaging the ltc3567 during a hot insertion,
ltc3567 24 3567f applications information figure 4. ntc circuits it is best to have a low voltage coef? cient capacitor at the v bus pin to the ltc3567. this is achievable by selecting an mlcc capacitor that has a higher voltage rating than that required for the application. for example, a 16v, x5r, 10f capacitor in a 1206 case would be a more conservative choice than a 6.3v, x5r, 10f capacitor in a smaller 0805 case. the size of the input overshoot will be determined by the q of the resonant tank circuit formed by c in and the input lead inductance. it is recommended to measure the input ringing with the selected components to verify compliance with the absolute maximum speci? cations. alternatively, the following soft connect circuit (figure 5) can be employed. in this circuit, capacitor c1 holds mp1 off when the cable is ? rst connected. eventually c1 begins to charge up to the usb input voltage applying increasing gate support to mp1. the long time constant of r1 and c1 prevent the current from building up in the cable too fast thus dampening out any resonant overshoot. figure 5. usb soft connect circuit scale output voltage is programmed using a resistor divider from the v out1 pin connected to the fb1 pin such that: v out1 = v fb1 r1 r f b + 1 where v fb1 ranges from 0.425v to 0.8v (see figure 6). closing the feedback loop the ltc3567 incorporates voltage mode pwm control. the control to output gain varies with operation region (buck, boost, buck-boost), but is usually no greater than 20. the output ? lter exhibits a double pole response given by: f filter _pole = 1 2? ?l?c out hz where c out is the output ? lter capacitor. the output ? lter zero is given by: f filter _ zero = 1 2? ?r esr ?c out hz where r esr is the capacitor equivalent series resistance. a troublesome feature in boost mode is the right-half plane zero (rhp), and is given by: f rhpz = v in1 2 2? ?i out ?l?v out1 hz the loop gain is typically rolled off before the rhp zero frequency. C + C + r nom 100k r ntc 100k ntc 0.017 ? v bus ntc_enable 3567 f04a ltc3567 ntc block (a) too_cold too_hot 0.765 ? v bus 0.349 ? v bus C + 3 v bus v bus C + C + r nom 105k r ntc 100k r1 12.7k ntc v bus v bus ntc_enable 3567 f04b too_cold too_hot 0.765 ? v bus 0.349 ? v bus C + 3 ltc3567 ntc block (b) 0.017v ? v bus r1 40k 5v usb input 3567 f05 c1 100nf c2 10f mp1 si2333 usb cable v bus gnd ltc3567 buck-boost regulator output voltage programming the buck-boost regulator can be programmed for output voltages greater than 2.75v and less than 5.5v. the full-
ltc3567 25 3567f applications information a simple type i compensation network (as shown in figure 6) can be incorporated to stabilize the loop but at the cost of reduced bandwidth and slower transient re- sponse. to ensure proper phase margin, the loop must cross unity-gain a decade before the lc double pole. figure 6. error ampli? er with type i compensation figure 7. error ampli? er with type iii compensation attempting to cross over after the lc double pole, the system must still cross over before the boost right-half plane zero. if unity gain is not reached suf? ciently before the right-half plane zero, then the C180 of phase lag from the lc double pole combined with the C90 of phase lag from the right-half plane zero will result in negating the phase bump of the compensator. the compensator zeros should be placed either before or only slightly after the lc double pole such that their positive phase contributions offset the C180 that occurs at the ? lter double pole. if they are placed at too low of a frequency, they will introduce too much gain to the system and the crossover frequency will be too high. the two high frequency poles should be placed such that the system crosses unity gain during the phase bump introduced by the zeros and before the boost right-half plane zero and such that the compensator bandwidth is less than the bandwidth of the error amp (typically 900khz). if the gain of the compensation network is ever greater than the gain of the error ampli? er, then the error ampli? er no longer acts as an ideal op-amp, and another pole will be introduced at the same point. recommended type iii compensation components for a 3.3v output: r1: 324k r fb : 105k c1: 10pf r2: 15k c2: 330pf r3: 121k c3: 33pf c out : 22f l out : 2.2h printed circuit board layout considerations in order to be able to deliver maximum current under all conditions, it is critical that the exposed pad on the backside of the ltc3567 package be soldered to the pc board ground. failure to make thermal contact between the unity-gain frequency of the error ampli? er with the type i compensation is given by: f ug = 1 2? ?r1?c p1 hz most applications demand an improved transient response to allow a smaller output ? lter capacitor. to achieve a higher bandwidth, type iii compensation is required. two zeros are required to compensate for the double-pole response. type iii compensation also reduces any v out1 overshoot seen at start-up. the compensation network depicted in figure 7 yields the transfer function: v c1 v out 1 = 1 r1? (c1 + c2 ) ? (1 + sr2c2) ? (1 + s(r1 + r3)c3) s? 1 + sr2c1c2 c1 + c 2 ?(1 + sr3c3 ) r1 r fb 3567 f06 0.8v fb1 v c1 c p1 v out1 C + error amp r1 c3 r fb 3567 f07 0.8v fb1 v c1 c2 r2 v out1 C + error amp c1 r3 a type iii compensation network attempts to introduce a phase bump at a higher frequency than the lc double pole. this allows the system to cross unity gain after the lc double pole, and achieve a higher bandwidth. while
ltc3567 26 3567f applications information the exposed pad on the backside of the package and the copper board will result in higher thermal resistances. furthermore, due to its high frequency switching cir- cuitry, it is imperative that the input capacitors, induc- tors, and output capacitors be as close to the ltc3567 as possible and that there be an unbroken ground plane under the ltc3567 and all of its external high frequency components. high frequency currents, such as the v bus , v in1 , and v out1 currents on the ltc3567, tend to ? nd their way along the ground plane in a myriad of paths ranging from directly back to a mirror path beneath the incident path on the top of the board. if there are slits or cuts in the ground plane due to other traces on that layer, the current will be forced to go around the slits. if high frequency currents are not allowed to ? ow back through their natural least-area path, excessive voltage will build up and radiated emissions will occur. there should be a group of vias under the grounded backside of the pack- age leading directly down to an internal ground plane. to minimize parasitic inductance, the ground plane should be on the second layer of the pc board. figure 8. higher frequency ground currents follow their incident path. slices in the ground plane cause high voltage and increased emissions. when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3567. 1. are the capacitors at v bus , v in1 , and v out1 as close as possible to the ltc3567? these capacitors provide the ac current to the internal power mosfets and their drivers. minimizing inductance from these capacitors to the ltc3567 is a top priority. 2. are c out and l1 closely connected? the (-) plate of c out returns current to the gnd plane, and then back to c in . 3. keep sensitive components away from the sw pins. battery charger stability considerations the ltc3567s battery charger contains both a constant- voltage and a constant-current control loop. the constant- voltage loop is stable without any compensation when a battery is connected with low impedance leads. excessive lead length, however, may add enough series inductance to require a bypass capacitor of at least 1f from bat to gnd. furthermore, when the battery is disconnected, a 4.7f capacitor in series with a 0.2 to 1 resistor from bat to gnd is required to keep ripple voltage low. high value, low esr multilayer ceramic chip capacitors reduce the constant-voltage loop phase margin, possibly resulting in instability. ceramic capacitors up to 22f may be used in parallel with a battery, but larger ceramics should be decoupled with 0.2 to 1 of series resistance. in constant-current mode, the prog pin is in the feed- back loop rather than the battery voltage. because of the additional pole created by any prog pin capacitance, capacitance on this pin must be kept to a minimum. with no additional capacitance on the prog pin, the battery charger is stable with program resistor values as high as 25k. however, additional capacitance on this node re- duces the maximum allowed program resistor. the pole frequency at the prog pin should be kept above 100khz. therefore, if the prog pin has a parasitic capacitance, c prog , the following equation should be used to calculate the maximum resistance value for r prog : r prog 1 2 ? 100khz ? c prog the gate pin for the external ideal diode controller has extremely limited drive current. care must be taken to minimize leakage to adjacent pc board traces. 100na of leakage from this pin will introduce an offset to the 15mv ideal diode of approximately 10mv. to minimize leakage, the trace can be guarded on the pc board by surrounding it with v out connected metal, which should generally be less than one volt higher than gate. 3567 f08
ltc3567 27 3567f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description typical applications + li-ion 100k 2.2 f c2 22 f c3 22 f 105k l1 3.3 h l2 2.2 h 33pf 121k 15k 3.01k 0.1f 2k c1 10 f 100k 1 f parts list c1: murata grm21br61a/06ke19 c2,c3: taiyo-yuden jmk212bj226mg l1: coilcraft lps4018-332mlc l2: coilcraft lps4018-222mlc usb 4.5v to 5.5v to other loads 3567 ta02 v bus ntc prog clprog ldo3v3 d vcc chrgen sw v out gate bat gnd chrg v in1 swab1 swcd1 v out1 fb1 v c1 en1 gnd ltc3567 i 2 c t 10pf 330pf 324k 3.3v/1a disk drive optional 2 1k push button microcontroller 4.00 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 24 23 1 2 bottom viewexposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (uf24) qfn 0105 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697 rev b) direct pin controlled ltc3567 usb power manager with 3.3v/1a buck-boost
ltc3567 28 3567f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0608 ? printed in usa related parts part number description comments ltc3440 600ma (i out ), 2mhz synchronous buck-boost dc/dc converter v in : 2.5v to 5.5v, v out : 2.5v to 5.5v i q = 25a, i sd < 1a, ms, dfn package ltc3441/ ltc3442 1.2a (i out ), synchronous buck-boost dc/dc converters, ltc3441 (1mhz), ltc3443 (600khz) v in : 2.5v to 5.5v, v out : 2.4v to 5.25v i q = 25a, i sd < 1a, ms, dfn package ltc3442 1.2a (i out ), 2mhz synchronous buck-boost dc/dc converter v in : 2.4v to 5.5v, v out : 2.4v to 5.25v i q = 28a, i sd < 1a, ms package ltc3455 dual dc/dc converter with usb power management and li-ion battery charger ef? ciency >96%, accurate usb current limiting (500ma/100ma), 4mm 4mm qfn-24 package ltc3538 800ma, 2mhz synchronous buck-boost dc/dc converter v in : 2.4v to 5.5v, v out : 1.8v to 5.25v i q = 35a, 2mm 3mm dfn-8 package ltc3550 dual input usb/ac adapter li-ion battery charger with adjustable output 600ma buck converter synchronous buck converter, ef? ciency: 93%, adjustable output at 600ma; charge current: 950ma programmable, usb compatible, automatic input power detection and selection, 3mm 5mm dfn-16 package ltc3550-1 dual input usb/ac adapter li-ion battery charger with 600ma buck converter synchronous buck converter, ef? ciency: 93%, output: 1.875v at 600ma; charge current: 950ma programmable, usb compatible, automatic input power detection and selection, 3mm 5mm dfn-16 package ltc3555 switching usb power manager with li-ion/polymer charger, triple synchronous buck converter plus ldo complete multi-function pmic: switchmode power manager and three buck regulators plus ldo; charge current programmable up to 1.5a from wall adapter input, thermal regulation synchronous buck converters ef? ciency: >95%, adj outputs: 0.8v to 3.6v at 400ma/400ma/1a bat-track adaptive output control, 200m ideal diode, 4mm 5mm qfn-28 package ltc3556 switching usb power manager with li-ion/polymer charger, 1a buck-boost plus dual sync buck converter plus ldo complete multi-function pmic: switching power manager, 1a buck-boost plus 2 buck regulators plus ldo, adj out down to 0.8v at 400ma/400ma/1a, synchronous buck/buck-boost converter ef? ciency: >95%; charge current programmable up to 1.5a from wall adapter input, thermal regulation, bat-track adaptive output control, 180m ideal diode, 4mm 5mm qfn-28 package ltc3557/ ltc3557-1 usb power manager with li-ion/polymer charger, triple synchronous buck converter plus ldo complete multi-function pmic: linear power manager and three buck regulators charge current programmable up to 1.5a from wall adapter input, thermal regulation synchronous buck converters ef? ciency: >95%, adj output: 0.8v to 3.6v at 400ma/400ma/600ma bat-track adaptive output control, 200m ideal diode, 4mm 4mm qfn-28 package ltc3559 linear usb li-ion/polymer battery charger with dual synchronous buck converter adjustable synchronous buck converters, ef? ciency: >90%, outputs: down to 0.8v at 400ma for each, charge current programmable up to 950ma, usb compatible, 3mm 3mm qfn-16 package ltc3566 switching usb power manager with li-ion/polymer charger, 1a buck-boost converter plus ldo multi-function pmic: switchmode power manager and 1a buck-boost regulator plus ldo, charge current programmable up to 1.5a from wall adapter input, thermal regulation synchronous buck-boost converters ef? ciency: >95%, adj output: down to 0.8v at 1a, bat-track adaptive output control, 180m ideal diode, 4mm 4mm qfn-24 package ltc4055 usb power controller and battery charger charges single-cell li-ion batteries directly from usb port, thermal regulation, 4mm 4mm qfn-16 package ltc4067 linear usb power manager with ovp , ideal diode controller and li-ion charger 13v overvoltage transient protection, thermal regulation 200m ideal diode with <50m option, 3mm 4mm qfn-14 package ltc4085 linear usb power manager with ideal diode controller and li-ion charger charges single cell li-ion batteries directly from a usb port, thermal regulation, 200m ideal diode with <50m option, 3mm 4mm qfn-14 package ltc4088 high ef? ciency usb power manager and battery charger maximizes available power from usb port, bat-track, instant-on operation, 1.5a maximum charge current, 180m ideal diode with <50m option, 3.3v/25ma always-on ldo, 3mm 4mm dfn-14 package ltc4088-1/ ltc4088/2 high ef? ciency usb power manager and battery charger with regulated output voltage maximizes available power from usb port, bat-track, instant-on operation, 1.5a maximum charge current, 180m ideal diode with <50m option, automatic charge current reduction maintains 3.6v minimum v out , battery charger disabled when all logic inputs are grounded, 3mm 4mm dfn-14 package

▲Up To Search▲

Price & Availability of LTC3567EUF-PBF

	To Download LTC3567EUF-PBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .